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s3c821a/p821a product overview 1 - 1 1 product overview s3c8-series microcontrolles samsung's s3c8 series of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programmable rom sizes. among the major cpu features ar e: ? efficient register-oriented architecture ? selectable cpu clock sources ? idle and stop power-down mode release by interrupt ? built-in basic timer with watchdog function a sophisticated interrupt structure recognizes up to eight interrupt levels. each level can have one or more interrupt sources and vectors. fast interrupt processing (within a minimum of six cpu clocks) can be assigned to specific interrupt levels. s3c821a/p821a microcontroller the s3c821a/p821a single-chip cmos microcontroller is fabricated using the highly advanced cmos process, based on samsung?s newest cpu architecture . the s3c821a is a microcontroller with a 48-kbyte mask-programmable rom embedded. the s3p821a is a microcontroller with a 48-kbyte one-time-programmable rom embedded. using a proven modular design approach, samsung engineers have successfully developed the s3c821a/p821a by integrating the following peripheral modules with the powerful sam8 core : ? six programmable i/o ports, including five 8-bit ports and one 7-bit port, for a total of 47 pins. ? twelve bit-programmable pins for external interrupts. ? one 8-bit basic timer for oscillation stabilization and watchdog functions (system reset) . ? one 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes. ? watch timer for real time. ? 4-input a/d converter ? serial i/o interface the s3c821a/p821a is versatile microcontroller for cordless phone, pager, etc. they are currently available in 80-pin tqfp and 80-pin qfp package. otp the s3p821a is an otp (one time programmable) version of the s3c821a microcontroller. the s3p821a microcontroller has an on-chip 48-kbyte one-time-programmable eprom instead of a masked rom. the s3p821a is comparable to the s3c821a, both in function and in pin configuration.
product overview s3c821a/p821a 1 - 2 feature s cpu ? sam8 cpu core memory ? data memory: 1040- byte of internal register file (excluding lcd ram) ? program memory: 48 -kbyte internal program memory (rom ) external interface ? 64-kbyte external data memory area instruction execution time ? 750 n s at 8 mhz (minimum, main oscillator) ? 183 m s at 32,768 hz (minimum, sub oscillator) interrupts ? 7 interrupt levels and 19 interrupt sources ? 19 vectors ? fast interrupt processing feature (for one selected interrupt level) i/o ports ? five 8-bit i/o ports (p0?p4) and one 7-bit i/o port (p5) for a total of 47 bit-programmable pins 8-bit basic timer ? one p rogrammable 8-bit basic timer (bt) for oscillation stabilization control or watchdog timer (software reset) function watch timer ? time internal generation: 3.91 ms, 0.5 s at 32,768 hz ? four frequency outputs to buz pin ? clock source generation for lcd timer s and timer/counters ? one 8-bit timer/counter (timer 0) with three operating modes: interval, capture, and pwm ? one 16-bit timer/counter (timer 1) with two 8-bit timer/counter modes lcd controller/driver ? up to 32 segment pins ? 3, 4, and 8 common selectable ? choice of duty cycle ? all dots can be switched on/off ? internal resistor circuit for lcd bias serial port ? one synchronous sio a/d converter ? 8-bit conversion resolution 4 channel ? 34 m s conversion time (4 mhz cpu clock, fxx/4) oscillation sources ? crystal, ceramic, or rc for main system clock ? crystal or external oscillator for subsystem clock ? main system clock frequency: 8 mhz ? subsystem clock frequency: 32.768 khz power-down modes ? main idle mode (only cpu clock stops) ? sub idle mode ? stop mode (main/sub system oscillation stops) operating temperature range ? ? 4 0 c to + 85 c operating voltage range ? 2.0 v to 5.5 v at 32 khz (sub clock)-6 mhz (main clock) ? 2.2 v to 5.5 v at 8 mhz package type ? 80-pin tqfp, 80-pin qfp
s3c821a/p821a produc t overview 1 - 3 block diagram i/o port and interrupt control sam8 cpu internal bus port 3 48 -kb rom 1-k byte register file port 0 p1.0-p1.7 port 1 timer 0 sio port 4 p0.0-p0.7 lcd driver com0-com3 seg0-seg3/ com4 - c om7 seg4 - seg31 vlc1 t1ck ta tb buz sck si so watch timer reset main osc sub osc timer 1 a and b a/d converter port 5 p2.0-p2.7 port 2 p3.0-p3.7 p4.0-p4.7 p5.0-p5.6 v dd 1 (internal) v ss 1 (internal) v dd 2 (external) v ss 2 (external) adc0 - adc3 a v ss a v ref t0ck t0/t0cap/ t0pwm x in x o ut x in x o ut figure 1-1. s3c821a simplified block diagram
product overview s3c821a/p821a 1 - 4 pin assignments p1.1/seg25/ad1 p1.2/seg26/ad2 p1.3/seg27/ad3 p1.4/seg28/ad4 p1.5/seg29/ad5 p1.6/seg30/ad6 p1.7/seg31/ad7 p2.0/ as p2.1/ dr v dd1 (int) v ss1 x out x in test xt in xt out reset p2.2/ dw p2.3/ dm p2.4/int0/t0ck s3c821a (80-tqfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 65 64 63 62 61 60 p2.5/int1/t1ck p2.6/int2/ta p2.7/int3/tb av ref p3.0/adc0 p3.1/adc1 p3.2/adc2 p3.3/adc3 av ss p3.4 p3.5 p3.6 p3.7/t0/t0pwm/t0cap p4.0/int4 p4.1/int5 p4.2/int6 p4.3/int7 p4.4/int8 p4.5/int9 p4.6/int10 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 seg4 seg3/com7 seg2/com6 seg1/com5 seg0/com4 com3 com2 com1 com0 v dd2 (ext) v ss2 v lc1 p5.6 p5.5 p5.4 p5.3/buz p5.2/so p5.1/si p5.0/sck p4.7/int11 p1.0/seg24/ad0 p0.7/seg23/a15 p0.6/seg22/a14 p0.5/seg21/a13 p0.4/seg20/a12 p0.3/seg19/a11 p0.2/seg18/a10 p0.1/seg17/a9 p0.0/seg16/a8 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 figure 1-2. s3c821a pin assignments (80-tqfp-1212)
s3c821a/p821a produc t overview 1 - 5 p0.6/seg22/a14 p0.5/seg21/a13 p0.4/seg20/a12 p0.3/seg19/a11 p0.2/seg18/a10 p0.1/seg17/a9 p0.0/seg16/a8 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 p0.7/seg23/a15 p1.0/seg24/ad0 p1.1/seg25/ad1 p1.2/seg26/ad2 p1.3/seg27/ad3 p1.4/seg28/ad4 p1.5/seg29/ad5 p1.6/seg30/ad6 p1.7/seg31/ad7 p2.0/ as p2.1/ dr v dd1 (int) v ss1 x out x in test xt in xt out reset p2.2/ dw p2.3/ dm p2.4/int0/t0ck p2.5/int1/t1ck p2.6/int2/ta s3c821a (80-qfp) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p2.7/int3/tb av ref p3.0/adc0 p3.1/adc1 p3.2/adc2 p3.3/adc3 av ss p3.4 p3.5 p3.6 p3.7/t0/t0pwm/t0cap p4.0/int4 p4.1/int5 p4.2/int6 p4.3/int7 p4.4/int8 seg6 seg5 seg4 seg3/com7 seg2/com6 seg1/com5 seg0/com4 com3 com2 com1 com0 v dd2 (ext) v ss2 v lc1 p5.6 p5.5 p5.4 p5.3/buz p5.2/so p5.1/si p5.0/sck p4.7/int11 p4.6/int10 p4.5/int9 figure 1-3. s3c821a pin assignments (80-qfp-1420c)
product overview s3c821a/p821a 1 - 6 pin descriptions table 1 - 1. s3c821a pin descriptions pin names pin type pin description circuit type pin numbers (note) share pins p0.0 ?p0.7 i/o 4-bit -programmable i/o port . pull-up resistors and open-drain outputs are software assignable . pull-up resistors are automatically disabled for output pins . configurable as lcd segments/ external interface address and data lines h-32 72?79 (74-80, 1) seg16/a8 ? seg23/a15 p1.0 ?1.7 i /o 4-bit -programmable i/o port . pull-up resistors and open-drain outputs are software assignable . pull-up resistors are automatically disabled for output pins . configurable as lcd segments/ external interface address and data lines h-32 80, 1?7 (2-9) seg24/ad0 ? seg31/ad7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2. 7 i/o 1-b it-programmable i/o port . pull-up resistors are software assignable , and automatically disabled for output pins . p2.0?p2.3 can alternately be used as external interface lines. p2.4?p2.7 are configurable as alternate functions or external interrupts at falling edge with noise filters. d-4 8 (10) 9 (11) 18 (20) 19 (21) 20 (22) 21 (23) 22 (24) 23 (25) as dr dw dm int0/t0ck int1/t1ck int2/ta int3/tb p 3 .0 ?p3.3 p3.4?p3.6 p3.7 i/o 1-b it-programmable i/o port . pull-up resistors are software assignable , and automatically disabled for output pins . p3.0?p3.3 can alternately be used as adc. p3.7 is configurable as an alternate function. f-16 d-4 d-4 25?28 (27?30) 30?32 (32?34) 33 (35) adc0?adc3 t0/t0pwm/ t0cap p 4 .0 ? p 4 . 7 i/o 1-b it-programmable i/o port . pull-up resistors and open-drain outputs are software assignable . pull-up resistors are automatically disabled for output pins . p4.0?p4.7 are configurable as external interrupts at a selectable edge with noise filters. e-4 34?41 (36?43) int4?int11 p 5 .0 p5.1 p5.2 p5.3 p5.4?p5.6 i/o 1-b it-programmable i/o port . pull-up resistors are software assignable , and automatically disabled for output pins . p5.0?p5.3 are configurable as alternate functions. if sck and si are used as input, these pins have noise filters. d-4 42 (44) 43 (45) 44 (46) 45 (47) 46?48 (48?50) sck si so buz note: parentheses indicate pin number for 80-qfp package.
s3c821a/p821a produc t overview 1 - 7 table 1 - 1. s3c821a pin descriptions (continued) pin names pin type pin description circuit type pin numbers (note) share pins v ss1 , v dd1 ? power input pins for internal power block ? 10, 11 (12, 13) ? x out , x in ? main oscillator pins ? 12, 13 (14, 15) ? test ? chip test input pin hold gnd when the device is operating ? 14 (16) ? xt in , xt out ? sub oscillator pins for sub-system clock ? 15, 16 (17,18) ? reset i reset signal input pin. schmitt trigger input with internal pull-up resistor. b 17 (19) ? int0?int3 i/o external interrupts input with noise filter. d-4 20?23 (22?25) p2.4?p2.7 t0ck i/o 8bit timer 0 external clock input. d-4 20 (22) p2.4 t1ck i/o timer 1/a external clock input. d-4 21 (23) p2.5 ta i/o timer 1/a clock output d-4 22 (24) p2.6 tb i/o timer b clock output d-4 23 (25) p2.7 t0 i/o timer 0 clock output d-4 33 (35) p3.7 t0pwm i/o timer 0 pwm output d-4 33 (35) p3.7 t0cap i/o timer 0 capture input d-4 33 (35) p3.7 adc0?adc3 i/o analog input pins for a/d converts module f-16 25?28 (27?30) p3.0?p3.3 av ref , av ss ? a/d converter reference voltage and ground ? 24, 29 (26, 31) ? int4?int11 i/o external interrupts input with noise filter. e-4 34?41 (36?43) p4.0?p4.7 buz i/o buzzer signal output d-4 45 (47) p5.3 sck, si, so i/o serial clock, serial data input, serial data output d-4 42?44 (44?46) p5.0?p5.2 v lc1 ? lcd bias voltage input pins ? 49 (51) ? v ss2 , v dd2 ? power input pins for external power block ? 50, 51 (52, 53) ? com0?com3 o lcd common signal output h-30 52?55 (54?57) ? seg0?seg3 (com4?com7) o lcd common or segment signal output h-31 56?59 (58?61) ? seg4?seg15 o lcd segment signal output h-29 60?71 (62?73) ? note: parentheses indicate pin number for 80-qfp package.
product overview s3c821a/p821a 1 - 8 table 1 - 1. s3c821a pin descriptions (continued) pin names pin type pin description circuit type pin numbers share pins seg16? seg23 i/o lcd segment signal output h-32 72?79 (74?80, 1) p0.0?p0.7 seg24? seg31 i/o lcd segment signal output h-32 80, 1?7 (2?9) p1.0?p1.7 a8?a15 i/o external interface address lines h-32 72?79 (74?80, 1) p0.0?p0.7 ad0?ad7 i/o external interface address/data lines h-32 80, 1?7 (2?9) p1.0?p1.7 as i/o address strobe d-4 8 (10) p2.0 dr i/o data read d-4 9 (11) p2.1 dw i/o data write d-4 18 (20) p2.2 dm i/o data memory select d-4 19 (21) p2.3 note: parentheses indicate pin number for 80-qfp package.
s3c821a/p821a produc t overview 1 - 9 pin circuits v dd p - channel n - channel in put figure 1- 4 . pin circuit type a pull-up resistor reset noise filter v dd figure 1- 5 . pin circuit type b output v ss data output disable v dd figure 1- 6 . pin circuit type c pull-up enable data output disable schmitt triger i/o v dd circuit type c figure 1- 7 . pin circuit type d-4
product overview s3c821a/p821a 1 - 10 pull-up resistor v dd i/o v ss open-drain en pull-up enable output disable v dd data figure 1 -8 . pin circuit type e-4 pull-up enable data output disable i/o v dd circuit type c data aden adselect t0 adc figure 1 -9 . pin circuit type f-16
s3c821a/p821a produc t overview 1 - 11 v lc1 v lc3 v ss v lc4 output figure 1 - 1 0. pin circuit type h-29 v lc1 v lc2 v ss v lc5 output figure 1-1 1. pin circuit type h-30 v lc1 v lc2 output v lc3 v lc4 v lc5 v ss figure 1-1 2. pin circuit type h-31
product overview s3c821a/p821a 1 - 12 pull-up resistor v dd i/o pull-up enable v ss output disable v dd data seg circuit type h-29 lcd out en open-drain en figure 1-1 3. pin circuit type h-32
s3c821a/p821a electrical data 17- 1 1 7 electrical data overview in this section, s3c821a electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? d.c. electrical characteristics ? data retention supply voltage in stop mode ? stop mode release timing when initiated by an external interrupt ? stop mode release timing when initiated by a reset ? i/o capacitance ? a.c. electrical characteristics ? a /d converter electrical characteristics ? input timing for external interrupts (p4, p2.4?p2.7) ? input timing for reset ? serial data transfer timing ? oscillation characteristics ? oscillation stabilization time ? operating voltage range
electrical data s3c821a/p821a 17- 2 table 17- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v in all i/o ports ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o port active ? 18 ma all i/o ports active ? 60 output current low i ol one i/o port active + 30 (peak value) ma + 15 (note) ports 0, 1, 2, and 3 + 100 (peak value) + 60 (note) ports 4 and 5 + 100 (peak value) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note: the values for output current low (i ol ) are calculated as peak value duty .
s3c821a/p821a electrical data 17- 3 table 17- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit operating voltage v dd f osc = 8 mhz (instruction clock = 1.33 mhz) 2.2 ? 5.5 v f osc = 6 mhz (instruction clock = 1 mhz) 2.0 input high voltage v ih1 p0 and p1 0.7 v dd ? v dd v v ih2 reset , p2, p3, p4, and p5 0.8 v dd v dd v ih3 x in , x t in v dd ? 0.1 v dd input low voltage v il1 p0 and p1 0 ? 0.3 v dd v il2 reset , p2, p3, p4, and p5 0.2 v dd v il3 x in , x t in 0.1 output high voltage v oh v dd = 3 v; i oh = ? 200 m a all output pins v dd ? 1.0 ? ? output low voltage v ol v dd = 3 v; i o l = 1 ma all output pins ? 0.4 1.0 input high leakage current i lih1 v i n = v dd all input pins except those specified below for i lih2 ? ? 1 a i lih2 v in = v dd x in , x out , xt in , and xt out 20 input low leakage current i lil1 v i n = 0 v all input pins except those specified below for i lil2 and reset ? ? ? 1 i lil2 v i n = 0 v x in , x out , xt in , and xt out ? 20 output high leakage current i loh v out = v dd all output pins ? ? 1 output low leakage current i lol v out = 0 v all output pins ? ? ? 1 | v dd ? comi | voltage drop (i = 0?7) v dc v dd = 2.7 v to 5.5 v ? 15 m a per common pin ? ? 120 mv | v dd ? segx | voltage drop (x = 0?31) v ds v lcd = 2.7 v to 5.5 v ? 15 m a per segment pin ? ? 120
electrical data s3c821a/p821a 17- 4 table 17- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit v lc2 output voltage v lc2 v dd = 2.7 v to 5.5 v lcd clock = 0 hz 0.8 v dd ? 0.15 0.8 v dd 0.8 v dd + 0.15 v v lc3 output voltage v lc3 v lc1 = v dd 0.6 v dd ? 0.15 0.6 v dd 0.6 v dd + 0.15 v lc4 output voltage v lc4 0.4 v dd ? 0.15 0.4 v dd 0.4 v dd + 0.15 v lc5 output voltage v lc5 0.2 v dd ? 0.15 0.2 v dd 0.2 v dd + 0.15 pull-up resistors r l1 v in = 0 v; t a = 25 c v dd = 3.0 10 %; ports 0?5 30 80 200 k w r l2 v in = 0 v; t a = 25 c v dd = 3.0 10 % reset only 200 450 800 lcd voltage dividing resistor r lcd v lcd = 2.7 v to 5.5 v t a = 25 c 45 65 80 k w supply current i dd1 run mode; v dd = 5 .0v 10% 6.0 mhz ? 6.0 12 ma ( n ote) c rystal oscillator c1 = c2 = 22 pf 4.19 mhz 4.5 9.0 v dd = 3 .0 v 10 % 6.0 mhz 2.9 5.8 4.19 mhz 2.0 4.0 i dd2 idle mode; v dd = 5 .0 v 0 % 6.0 mhz 1.3 2.6 c rystal oscillator c1 = c2 = 22 pf 4.19 mhz 1.2 2.4 v dd = 3 .0 v 10 % 6.0 mhz 0.6 1.2 4.19 mhz 0.4 0.8 i dd 3 run mode; v dd = 3 .0 v 10 % 32 k hz crystal oscillator 20 40 a i dd 4 idle mode; v dd = 3 .0 v 10 % 32 k hz crystal oscillator 7 14 i dd 5 stop mode; v dd = 5 .0 v 10 % 0.5 3 stop mode; v dd = 3 .0 v 10 % 0.3 2 note s : 1. supply current does not include current drawn through internal pull-up resistors , lcd voltage dividing resistors, and adc . 2. i dd1 and i dd2 include power consumption for subsystem clock oscillation. 3. i dd3 and i dd4 are current when main system clock oscillation stops and the subsystem clock is used. 4. i dd5 is current when main system clock and subsystem clock oscillation stops.
s3c821a/p821a electrical data 17- 5 table 17- 3. data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 2.2 ? 3.4 v data retention supply current i dddr v dddr = 1.0 v stop mode ? ? 1 a oscillator stabilization t wait released by reset ? 2 16 /fx (1) ? ms wait time released by interrupt ? (2) ? notes: 1. fx is the main oscillator frequency. 2. the duration of the oscillation stabilization time (t wait ) when it is released by an interrupt is determined by the setting in the basic timer control register, btcon. v dd interrupt request execution of stop instruction v dddr data retention mode stop mode normal operating mode t wait idle mode (basic timer active) ~ ~ 0.8 v dd ~ ~ figure 17- 1. stop mode release timing when initiated by a n external interrupt
electrical data s3c821a/p821a 17- 6 v dd reset execution of stop instruction v dddr data retention mode stop mode normal operating mode t wait oscillation stabilization time reset occurs 0.2 v dd 0.8 v dd ~ ~ ~ ~ figure 17-2 . stop mode release timing when initiated by a reset reset
s3c821a/p821a electrical data 17- 7 table 17-4. input/ o utput capacitance (t a = ? 25 c, v dd = 0 v) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are connected to v ss ? ? 10 pf output capacitance c out i/o capacitance c io table 17- 5. a.c. electrical characteristics (t a = ? 40 c to + 85 c , v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit sck cycle time t kcy external sck source 1,000 ? ? ns internal sck source 1,000 sck high, low t kh, t kl external sck source 500 width internal sck source t kcy /2?50 si setup time to t sik external sck source 250 sck high internal sck source 250 si hold time to t ksi external sck source 400 sck high internal sck source 400 output delay for t kso external sck source ? ? 300 ns sck to so internal sck source 250 interrupt input, high, low width t int h , t int l all interrupt v dd = 3 v 500 700 ? ns reset input low width t rsl input v dd = 3 v 2,0 00 ? ?
electrical data s3c821a/p821a 17- 8 table 17-6 . a/d converter electrical characteristics (t a = ? 4 0 c to + 85 c, v dd = 2.7 v to 5 . 5 v, v ss = 0 v) parameter symbol conditions min typ max unit resolution ? 8 ? bit total accuracy v dd = 5.12 v ? ? 2 lsb av ref = 5 .12 v av ss = 0 v conversion time ( 1 ) t con 8 bit conversion 34 x n/fxx (2) , n=1,4,8,16 17 ? 170 m s analog input voltage v ian ? av ss ? av ref v analog input impedance r an ? 2 1,000 ? m w analog reference voltage av ref ? 2.5 ? v dd v analog ground av ss ? v ss ? v ss + 0.3 v analog input current i adin av ref = v dd = 5 v ? ? 10 m a notes: 1. " conversion time " is the time required from the moment a conversion operation starts until it ends . 2 . fxx is a selected system clock for peripheral hardware.
s3c821a/p821a electrical data 17- 9 0.8 v dd 0.2 v dd t int l t int h note : the unit t cpu means one cpu clock period. figure 17-3 . input timing for external interrupts t rsl 0.2 v dd reset figure 17-4 . input timing for reset reset sck t kl t kh t kcy 0.8 v dd input data output data 0.2 v dd 0.8 v dd 0.2 v dd si so t kso t sik t ksi figure 17-5 . serial data transfer timing
electrical data s3c821a/p821a 17- 10 table 17-7 . main system osc illation characteristics (t a = ? 40 c + 85 c) oscillator clock circuit parameter condition (v dd ) min typ max unit crystal c2 c1 x in x out main oscillation frequency 2.2 v?5.5 v 0.4 ? 8 mhz 2.0 v?5.5 v 0.4 ? 6 ceramic c2 c1 x in x out main oscillation frequency 2.2 v?5.5 v 0.4 ? 8 2.0 v?5.5 v 0.4 ? 6 external clock x in x out x in input frequency 2.2 v?5.5 v 0.4 ? 8 2.0 v?5.5 v 0.4 ? 6 rc x in x out r frequency 3.0 v 0.4 ? 2 table 17-8 . subsystem oscillation characteristics (t a = ? 40 c + 85 c) oscillator clock circuit parameter condition (v dd ) min typ max unit crystal c2 c1 xt in xt out sub oscillation frequency 2.0 v?5.5 v 32 32.768 35 k hz external clock xt in xt out xt in input frequency 2.0 v?5.5 v 32 ? 500 k hz
s3c821a/p821a electrical data 17- 11 table 17-9 . main oscillation stabilization time (t a = ? 40 c + 85 c, v dd = 2.0 v to 5.5 v) oscillator test condition min typ max unit c rystal fx > 400 khz ? ? 20 ms c eramic oscillation stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 10 ms external clock x in input high and low width (t xh , t xl ) 25 ? 500 ns x in t xl t xh 1 / f x v dd ? 0.1 v 0.1 v figure 17-6. clock timing measurement at x in table 17-10 . sub oscillation stabilization time (t a = ? 40 c + 85 c, v dd = 2.0 v to 5.5 v) oscillator test condition min typ max unit c rystal ? ? ? 10 s external clock xt in input high and low width (t xh , t xl ) 1 ? 18 m s xt in t xtl t xth 1 / f xt v dd ? 0.1 v 0.1 v figure 17-7. clock timing measurement at xt in
electrical data s3c821a/p821a 17- 12 instruction clock = 1/6n x oscillator frequency (n = 1, 2, 8, 16) supply voltage (v) 1.00 mhz 8.33 khz instruction clock 2 3 7 f x (main oscillation frequency) 6 mhz 400 khz 8 mhz 2.2 5.5 1.33 mhz 1 5 4 6 figure 17-8. operating voltage range
s3c821a/p821a mecha nical data 18 - 1 1 8 mechanical data overview the s3c821a micr ocontroller is currently available in 80 -pin qfp and tqfp package. note : dimensions are in millimeters. 0.80 0.20 0.10 max 0.15 +0.10 - 0.05 0 - 8 2.65 0.10 3.00 max 0.05 min 17.90 0.3 14.00 0.2 (1.00) 80-qfp-1420c 23.90 0.3 #80 (0.80) #1 0.35 0.1 0.15 max 20.00 0.2 0.80 0.80 0.20 figure 18-1. 80- pin qf p package demensions
mechanical data s3c821a/p821a 18 - 2 note : dimensions are in millimeters. 14.00bsc 12.00bsc 80-tqfp-1212 14.00bsc 12.00bsc #80 (1.25) #1 0.17 - 0.27 0.60 0.15 0.09 - 0.20 0 - 7 1.00 0.05 1.20 max 0.05-0.15 0.08 max m 0.50 figure 18-2. 80- pin tqf p package demensions
s3c821a/p821a s3p821 a otp 20- 1 20 s3p821a otp overview the s3p821a single-chip cmos microcontroller is the otp (one time programmable) version of the s3c821a microcontroller. it has an on-chip otp rom instead of a masked rom. the eprom is accessed by serial data format. the s3p821a is fully compatible with the s3c821a, both in function and in pin configuration. because of its simple programming requirements, the s3p821a is ideal as an evaluation chip for the s3c821a.
s3p821a otp s3c821a/ p821a 20- 2 p1.1/seg25/ad1 p1.2/seg26/ad2 p1.3/seg27/ad3 p1.4/seg28/ad4 p1.5/seg29/ad5 p1.6/seg30/ad6 p1.7/seg31/ad7 sdat /p2.0/ as sclk /p2.1/ dr v dd1 /v dd1 v ss1 /v ss1 x out x in v pp /test xt in xt out reset/reset p2.2/ dw p2.3/ dm p2.4/int0/t0ck s3p821a (80-tqfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 65 64 63 62 61 60 p2.5/int1/t1ck p2.6/int2/ta p2.7/int3/tb av ref p3.0/adc0 p3.1/adc1 p3.2/adc2 p3.3/adc3 av ss p3.4 p3.5 p3.6 p3.7/t0/t0pwm/t0cap p4.0/int4 p4.1/int5 p4.2/int6 p4.3/int7 p4.4/int8 p4.5/int9 p4.6/int10 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 seg4 seg3/com7 seg2/com6 seg1/com5 seg0/com4 com3 com2 com1 com0 v dd2 (ext) v ss2 v lc1 p5.6 p5.5 p5.4 p5.3/buz p5.2/so p5.1/si p5.0/sck p4.7/int11 p1.0/seg24/ad0 p0.7/seg23/a15 p0.6/seg22/a14 p0.5/seg21/a13 p0.4/seg20/a12 p0.3/seg19/a11 p0.2/seg18/a10 p0.1/seg17/a9 p0.0/seg16/a8 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 figure 20-1. s3p821a pin assignments (80-tqfp-1212 package)
s3c821a/p821a s3p821 a otp 20- 3 p0.6/seg22/a14 p0.5/seg21/a13 p0.4/seg20/a12 p0.3/seg19/a11 p0.2/seg18/a10 p0.1/seg17/a9 p0.0/seg16/a8 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 p0.7/seg23/a15 p1.0/seg24/ad0 p1.1/seg25/ad1 p1.2/seg26/ad2 p1.3/seg27/ad3 p1.4/seg28/ad4 p1.5/seg29/ad5 p1.6/seg30/ad6 p1.7/seg31/ad7 sdat /p2.0/ as sclk /p2.1/ dr v dd1 /v dd1 v ss1 /v ss1 x out x in v pp /test xt in xt out reset reset /reset p2.2/ dw p2.3/ dm p2.4/int0/t0ck p2.5/int1/t1ck p2.6/int2/ta s3p821a (80-qfp) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p2.7/int3/tb av ref p3.0/adc0 p3.1/adc1 p3.2/adc2 p3.3/adc3 av ss p3.4 p3.5 p3.6 p3.7/t0/t0pwm/t0cap p4.0/int4 p4.1/int5 p4.2/int6 p4.3/int7 p4.4/int8 seg6 seg5 seg4 seg3/com7 seg2/com6 seg1/com5 seg0/com4 com3 com2 com1 com0 v dd2 (ext) v ss2 v lc1 p5.6 p5.5 p5.4 p5.3/buz p5.2/so p5.1/si p5.0/sck p4.7/int11 p4.6/int10 p4.5/int9 figure 20-2. s3p821a pin assignments (80-qfp-1420c package)
s3p821a otp s3c821a/ p821a 20- 4 table 20-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p2.0 sdat 8 (10) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. p2.1 sclk 9 (11) i/o serial clock pin. input only pin. v pp test 14 (16) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 17 (19) i chip initialization v dd1 /v ss1 v dd1 /v ss1 10 (12)/11 (13) ? logic power supply pin. v dd should be tied to + 5 v during programming. note: ( ) means 80 qfp package. table 20-2. comparison of s3p821a and s3c821a features characteristic s3p821a s3c821a program memory 48-k byte eprom 48-k byte mask rom operating voltage (v dd ) 2.0 v to 5.5 v 2.0 v to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5 v pin configuration 80 qfp/80 tqfp 80 qfp/80 tqfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the s3p821a, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 20-3 below. table 20-3. operating mode selection criteria v dd v pp ( test ) reg/ mem mem address (a15?a0) r/ w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note: "0" means low level ; "1" means high level.
s3c821a/p821a s3p821 a otp 20- 5 table 20-4 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit operating voltage v dd f osc = 8 mhz (instruction clock = 1.33 mhz) 2.2 ? 5.5 v f osc = 6 mhz (instruction clock = 1 mhz) 2.0 input high voltage v ih1 p0 and p1 0.7 v dd ? v dd v v ih2 reset, p2, p3, p4, and p5 0.8 v dd v dd v ih3 x in , x t in v dd ? 0.1 v dd input low voltage v il1 p0 and p1 0 ? 0.3 v dd v il2 reset, p2, p3, p4, and p5 0.2 v dd v il3 x in , x t in 0.1 output high voltage v oh v dd = 3 v; i oh = ? 200 m a all output pins v dd ? 1.0 ? ? output low voltage v ol v dd = 3 v; i o l = 1 ma all output pins ? 0.4 1.0 input high leakage current i lih1 v i n = v dd all input pins except those specified below for i lih2 ? ? 1 a i lih2 v in = v dd x in , x out , xt in , and xt out 20 input low leakage current i lil1 v i n = 0 v all input pins except those specified below for i lil2 and reset ? ? ? 1 i lil2 v i n = 0 v x in , x out , xt in , and xt out ? 20 output high leakage current i loh v out = v dd all output pins ? ? 1 output low leakage current i lol v out = 0 v all output pins ? ? ? 1 | v dd ? comi | voltage drop (i = 0-7) v dc v dd = 2.7 v to 5.5 v ? 15 m a per common pin ? ? 120 mv | v dd ? segx | voltage drop (x = 0-31) v ds v lcd = 2.7 v to 5.5 v ? 15 m a per segment pin ? ? 120
s3p821a otp s3c821a/ p821a 20- 6 table 20-4 . d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit v lc2 output voltage v lc2 v dd = 2.7 v to 5.5 v lcd clock = 0 hz 0.8 v dd ? 0.15 0.8 v dd 0.8 v dd + 0.15 v v lc3 output voltage v lc3 v lc1 = v dd 0.6 v dd ? 0.15 0.6 v dd 0.6 v dd + 0.15 v lc4 output voltage v lc4 0.4 v dd ? 0.15 0.4 v dd 0.4 v dd + 0.15 v lc5 output voltage v lc5 0.2 v dd ? 0.15 0.2 v dd 0.2 v dd + 0.15 pull-up resistors r l1 v in = 0 v; t a = 25 c v dd = 3.0 10%; ports 0?5 30 80 200 k w r l2 v in = 0 v; t a = 25 c v dd = 3.0 10 % reset only 300 500 800 lcd voltage dividing resistor r lcd v lcd = 2.7 v to 5.5 v t a = 25 c 45 65 80 k w supply current i dd1 run mode; v dd = 5 .0v 10% 6.0 mhz ? 6.0 12 ma ( n ote) c rystal oscillator c1 = c2 = 22 pf 4.19 mhz 4.5 9.0 v dd = 3 .0 v 10 % 6.0 mhz 2.9 5.8 4.19 mhz 2.0 4.0 i dd2 idle mode; v dd = 5 .0 v 0% 6.0 mhz 1.3 2.6 c rystal oscillator c1 = c2 = 22 pf 4.19 mhz 1.2 2.4 v dd = 3 .0 v 10 % 6.0 mhz 0.6 1.2 4.19 mhz 0.4 0.8 i dd 3 run mode; v dd = 3 .0 v 10 % 32 k hz crystal oscillator 20 40 a i dd 4 idle mode; v dd = 3 .0 v 10 % 32 k hz crystal oscillator 7 14 i dd 5 stop mode; v dd = 5 .0 v 10 % 0.5 3 stop mode; v dd = 3 .0 v 10 % 0.3 2 note s : 1. supply current does not include current drawn through internal pull-up resistors , lcd voltage dividing resistors, and adc . 2. i dd1 and i dd2 include power consumption for subsystem clock oscillation. 3. i dd3 and i dd4 are current when main system clock oscillation stops and the subsystem clock is used. 4. i dd5 is current when main system clock and subsystem clock oscillation stops.
s3c821a/p821a s3p821 a otp 20- 7 instruction clock = 1/6n x oscillator frequency (n = 1, 2, 8, 16) supply voltage (v) 1.00 mhz 8.33 khz instruction clock 2 3 7 f x (main oscillation frequency) 6 mhz 400 khz 8 mhz 2.2 5.5 1.33 mhz 1 5 4 6 figure 20-3. operating voltage range

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